1. Technical Field
This invention pertains to the field of information processing, particularly to the field of techniques for improving information processing efficiency and performance through dynamically adapting processing resource types to match processing task types.
2. Descriptions of the Related Art
Conventional data processing hardware comprises several types of processor cores, e.g. Central Processing Units (CPUs), Digital Signal Processors (DSPs), Graphics Processing Units (GPUs) etc. and variations thereof. These core types are often designed either for generic program processing, i.e., are not optimal for any specific types of processing task, or are designed for and optimal for a particular types of processing tasks. Consequently, for any given data processing job, processing hardware made of generic processors will likely be less efficient than processing hardware made of specialized processors designed for the demands of the given job. On the other hand, processing hardware made of specialized processors will have a narrower range of suitable jobs for which such a specialized hardware is reasonably efficient, compared to hardware made of generic processors.
Still, the range of processing jobs for a given instance of processing hardware (e.g. a server blade used for computing Infrastructure-as-a-Service), especially over the lifetime of the given hardware instance, may comprise several types of jobs and their tasks, with each type best suited for its corresponding, distinct, processor type. Moreover, an array of processing hardware units (e.g. server blades, and/or cores within them, supporting computing Infrastructure-as-a-Service contracts) will likely be used for processing several types of jobs and tasks, each best suited for their corresponding processor core types, even at the same time instance.
However, it will be quite infeasible to predict ahead of time, e.g. when a given instance of processing (having a hardware with a processor core or array of them) is deployed for service, to know what would be the optimal type of core for any given processor instance, or the optimal breakdown of core types for a given array of processors—even on average over the lifetime of such processor(s), or, more relevantly as well as challengingly still, at any given instance of time while such processors are in service.
Consequently, the time varying sets of processing jobs for their target processing hardware units will, using conventional techniques, in practice be processed often by suboptimal types of processing cores. This leads to low overall data processing efficiency, e.g., in forms of executing tasks on core types that are worse suited for a given task than another type of core would be, or poor processing capacity utilization due to mismatches between the types of active tasks (in terms of the cores best suited for a given set of active jobs) and the types of their execution cores. Consequences of such conventional techniques include suboptimal performance (e.g. in terms of time and/or energy taken to process given jobs) and low cost-efficiency (volume of program processing on-time throughput per unit cost) of application processing.
For related art, the reader is referred to referenced publications as follows:    [X1] Partial Reconfiguration User Guide, a Xilinx, Inc. user document UG702 (v14.2) Jul. 25, 2012. Source: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14—2/ug702.pdf (retrieved Nov. 29, 2012).    [X2] David Dye. Partial Reconfiguration of Xilinx FPGAs Using ISE Design Suite, a Xilinx, Inc. White Paper WP374 (v1.2), May 30, 2012. Source: http://www.xilinx.com/support/documentation/white_papers/wp374_Partial_Reconfig_Xilinx_FPGAs.pdf (retrieved Nov. 29, 2012).    [X3] Sébastien Lamonnier, Marc Thoris, Marlene Ambielle. Accelerate Partial Reconfiguration with a 100% Hardware Solution, Xcell Journal, Issue 79, Second Quarter 2012: pages 44-49. Source: http://www.xilinx.com/publications/archives/xcell/Xce1179.pdf (retrieved Nov. 28, 2012).    [X4] 7 Series FPGAs Configuration User Guide, a Xilinx, Inc. User Guide UG470 (v1.5) Nov. 5, 2012. Source: http://www.xilinx.com/support/documentation/user_guides/ug470—7Series_Config.pdf (retrieved Dec. 4, 2012).    [X5] Partial Reconfiguration Tutorial, PlanAhead Design Tool, a Xilinx, Inc. User Guide UG743 (v14.1) May 8, 2012. Source: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14—1/PlanAhead_Tutorial_Partial_Reconfiguration.pdf    [X6] Simon Tam, Martin Kellermann. Fast Configuration of PCI Express Technology through Partial Reconfiguration, a Xilinx, Inc. Application Note XAPP883 (v1.0) Nov. 19, 2010. Source: http://www.xilinx.com/support/documentation/application_notes/xapp883_Fast_Config_PCIe.pdf (retrieved Dec. 10, 2012).    [A1] Deshanand Singh. Implementing FPGA Design with the OpenCL Standard, an Altera corporation White Paper WP-01173-2.0, November 2012. Source: http://www.altera.com/literature/wp/wp-01173-opencl.pdf (retrieved Nov. 29, 2012).
The reference [X1] provides user documentation for reconfiguring portions of programmable logic chips. The references [X2], [X3], [X4], [X5] and [X6] discuss implementation techniques for, under the control of user logic, reconfiguring portions (slots) in programmable logic chips, such as the core slots of the herein disclosed manycore array, with identified alternative hardware logic functions, such as the differing processing core types discussed, e.g. Application Specific Processors (ASPs). The reference [A1] discusses techniques translating functions of software programs to custom hardware logic implementations, e.g. ASPs. More specifically, concerning reconfiguring the logic of parts of programmable logic devices or field programmable gate array microchips (FPGAs), [X2] discusses techniques for how the FPGA logic can control reconfiguring sub-areas of the FPGA, while [X3] details an implementation of an FPGA logic design to control an “Internal Configuration Access Port” (ICAP) of a Xilinx FPGA to reconfigure a particular area of the FPGA with an identified logic configuration bitstream; see in particular pp. 46-47 of the source journal of [X3] referring to the FIGS. 2 and 3 of the article, under its captions “Reconfiguration Process” and “Inside ICAP”. [X4] describes interacting with said ICAP (specifically, ICAPE2 in Xilinx Series 7 FPGAs) by user designed logic, including specifying a configuration bitstream (by its start address in a non-volatile memory storing multiple alternative full and/or partial configuration bitstreams) to be used for a (partial) reconfiguration of the FPGA; see in particular subsections ‘IPROG’ and ‘WBSTAR’ on pp. 122-123, and “IPROG Reconfiguration” and “IPROG Using ICAPE2” on pp. 124-125. [X5] provides documentation for creating partial reconfiguration logic programming bit files, while [X6] describes techniques for partial reconfiguration of the logic etc. in a defined sub-area of an FPGA chip, while keeping the functions of the chip not subject to any given partial reconfiguration process un-impacted during such partial reconfigurations. [A1] discusses an OpenCL compiler for translating software (C-language) program functions to hardware that implements each operation of such functions.
These related art publications however do not enable adapting the types of processing resources in a given resource pool according to the processing load and type demand variations presented by a group of applications configured to dynamically share the given pool of processing resources. Innovations are thus needed to accomplish that goal.